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Approximation of Decimation Filters Using the SMAC Architecture

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In a previous paper, the SMAC architecture has been demonstrated to perform third-order Lagrange polynomial interpolation with fewer DSP execution cycles. The features and constraints of the SMAC architecture are applied to an oversampled sine function to approximate a third-order decimation filter.

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Permalink: https://www.aes.org/e-lib/browse.cfm?elib=7187

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