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FPGA-Based Acceleration of FDTD Sound Field Rendering

Sound field rendering is computation-intensive and memory-intensive. This research investigates an FPGA-based accelerator for sound field rendering with an FDTD scheme, in which wave equations are directly implemented by reconfigurable hardware, and spatial blocking is applied to alleviate the memory bandwidth requirement. Compared to software simulation performed on a desktop machine with 128 GB DDR4 RAMs and an Intel i7-7820X processor running at 3.6 GHz, the proposed FPGA-based accelerator achieves up to 2.98 times more in computing performance in the case of different layer sizes and different numbers of nodes computed in parallel even though the FPGA system runs at about 267 MHz.

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JAES Volume 69 Issue 7/8 pp. 542-556; July 2021
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Permalink: http://www.aes.org/e-lib/browse.cfm?elib=21121

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AES - Audio Engineering Society