This paper details the design and implementation of a novel S/PDIF transceiver with a very low jitter bandwidth. We describe and demonstrate a system based on multiple-loops that synchronises to the incoming data stream with a very low bandwidth and provides the original data unmodified on a clean low jitter output clock without the need for a sample rate converter. Thus we eliminate any jitter above a low frequency (typically 10Hz) on the input data and also avoid any distortion caused by sample rate converters.
Click to purchase paper as a non-member or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member and would like to subscribe to the E-Library then Join the AES!
This paper costs $33 for non-members and is free for AES members and E-Library subscribers.