AES E-Library

AES E-Library

CMOS Self-Oscillating Class D Amplifier with Output Optimization

Simple amplifier topologies are not the norm for integrated circuit (IC) class D amplifiers. A simple self-oscillating topology [1] is mapped into a standard CMOS technology and fabricated in a 0.5 micron process. The output stage is optimized for a range of modulation indices [2], simultaneously increasing average efficiency and reducing chip area. Modifications to the optimization methodology are proposed to enhance efficiency and reduce the large transient currents inherent in CMOS inverter chains. Test results are presented and compared to predicted and simulated values. This project shows that design complexity is not requisite for good performance and high efficiency.

AES Convention: Paper Number:
Publication Date:

Click to purchase paper as a non-member or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member and would like to subscribe to the E-Library then Join the AES!

This paper costs $33 for non-members and is free for AES members and E-Library subscribers.

Learn more about the AES E-Library

E-Library Location:

Start a discussion about this paper!

AES - Audio Engineering Society