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Theory and VLSI Architectures for Asynchronous Sample-Rate Converters

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The theory of asynchronous sample-rate conversion is presented using both the highly interpolated signal-processing model as well as the polyphase filter model. A novel closed-loop address-tracking system is disclosed that solves the problem of clock-edge arrival estimation while at the same time providing a low-jitter selection of the correct polyphase filter for each sampling instant. The proposed signal-processing algorithm has been implemented in an all-digital VLSI chip. Measurement results show good agreement with theory.

JAES Volume 41 Issue 7/8 pp. 539-555; July 1993
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