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Theory and VLSI Implementation of Asynchronous Sample-Rate Converters

Asynchronous sample-rate conversion requires the solution to four major problems: clock time-of-arrival estimation, reduction of filter coefficients, RAM read/write pointer control, and dynamic filter adaptation for the undersampled case (FSout < FSin). Existing solutions to these problems involve multiple DSP chips with complicated external hardware. Design details of a new one-chip dedicated asynchronous sample-rate converter IC will be presented.

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