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Jitter Analysis of Asynchronous Sample-Rate Conversion

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Jitter has become a major limiting factor in the quality of D/A conversion. The extensive use of serial communications protocols forces the use of PLL-based clock recovery circuits which often produce unacceptable amounts of jitter. The sensitivity of various D/A conversion techniques to jitter varies widely and is often signal dependent. A new VLSI chip has been designed to solve the problem of asynchronous rate conversion between arbitrary frequencies. A servo-control loop with very long time constants has the effect of heavily low-pass filtering the jitter spectrum, which largely eliminates the effects of jitter on signal quality.

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Permalink: http://www.aes.org/e-lib/browse.cfm?elib=6520

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