A 2x40W integrated stereo sigma-delta class D amplifier with 100 dB SNR is realized in 0.6um BCDMOS technology. Feedback from power stage outputs gives 0.001% THD and 65dB PSRR. Modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak related to the hysteresis, but is otherwise tone-free, unlike PWM modulators which contain many harmonics of the PWM clock frequency.

Authors: Adams, Robert; Gaalaas, Eric; Liu, Bill Yang; Morajkar, Rajeev; Nishimura, Naoaki; Sweetland, Karl
Affiliation: Analog Devices Inc.
AES Convention: 118 (May 2005) Paper Number: 6452
Publication Date: May 1, 2005 Import into BibTeX
Subject: Signal Processing
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=13168

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