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This paper examines desirable architectural features of a new 32-bit single-instruction multiple-data (SIMD) digital signal processor (DSP) based on a modified Harvard architecture for implementation of real-time professional and consumer audio applications. The discussion begins by covering important audio processor-specific characteristics of this SIMD architecture, such as native data-word size, dynamic range/signal-to-noise ratio capabilities, memory organization, processor speed, performance benchmarks, and input/output (I/O) capabilities. We will then highlight a couple of example DSP audio algorithms to demonstrate the benefits of such an architecture, which can speed up algorithmic execution by as much as a factor of 5 over earlier single-instruction single-data SISD super-Harvard architectures (SHARC).
Author (s): Tomarakos, John;
Duggan, Colin;
Affiliation:
DSPApplications Group, Analog Devices, Norwood, MA
(See document for exact affiliation information.)
Publication Date:
2000-03-06
DOI:
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Tomarakos, John; Duggan, Colin; 2000; 32-Bit SIMD SHARC Architecture Digital Audio Signal Processing Applications [PDF]; DSPApplications Group, Analog Devices, Norwood, MA; Paper ; Available from: https://aes.org/publications/elibrary-page/?id=12071
Tomarakos, John; Duggan, Colin; 32-Bit SIMD SHARC Architecture Digital Audio Signal Processing Applications [PDF]; DSPApplications Group, Analog Devices, Norwood, MA; Paper ; 2000 Available: https://aes.org/publications/elibrary-page/?id=12071
@article{Tomarakos200032-bit,
title={{32-Bit SIMD SHARC Architecture Digital Audio Signal Processing Applications}},
author={Tomarakos, John and Duggan, Colin},
year={2000},
month={mar},
journal={Journal of the Audio Engineering Society},
volume={48},
number={3},
pages={220-222, 224-229},
}
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