32-Bit SIMD SHARC Architecture Digital Audio Signal Processing Applications
This paper examines desirable architectural features of a new 32-bit single-instruction multiple-data (SIMD) digital signal processor (DSP) based on a modified Harvard architecture for implementation of real-time professional and consumer audio applications. The discussion begins by covering important audio processor-specific characteristics of this SIMD architecture, such as native data-word size, dynamic range/signal-to-noise ratio capabilities, memory organization, processor speed, performance benchmarks, and input/output (I/O) capabilities. We will then highlight a couple of example DSP audio algorithms to demonstrate the benefits of such an architecture, which can speed up algorithmic execution by as much as a factor of 5 over earlier single-instruction single-data SISD super-Harvard architectures (SHARC).
Click to purchase paper as a non-member or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member and would like to subscribe to the E-Library then Join the AES!
This paper costs $33 for non-members and is temporarily free for AES members.