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32-Bit SIMD SHARC Architecture Digital Audio Signal Processing Applications

This paper examines desirable architectural features of a new 32-bit single-instruction multiple-data (SIMD) digital signal processor (DSP) based on a modified Harvard architecture for implementation of real-time professional and consumer audio applications. The discussion begins by covering important audio processor-specific characteristics of this SIMD architecture, such as native data-word size, dynamic range/signal-to-noise ratio capabilities, memory organization, processor speed, performance benchmarks, and input/output (I/O) capabilities. We will then highlight a couple of example DSP audio algorithms to demonstrate the benefits of such an architecture, which can speed up algorithmic execution by as much as a factor of 5 over earlier single-instruction single-data SISD super-Harvard architectures (SHARC).

Authors: Tomarakos, John; Duggan, Colin
Affiliation: DSPApplications Group, Analog Devices, Norwood, MA
JAES Volume 48 Issue 3 pp. 220-222, 224-229; March 2000 Import into BibTeX

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