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This paper describes a technique for designing a phase-linear digital audio octave stereo equalizer using a MC6809 microprocessor and a TRW TDC1010 multiplier-accumulator. The digital filter structure is composed of four parallel paths. Each path, consisting of a separate FIR filter implemented by a multiplier-accumulator, processes a distinct, non-overlapping segment of the audio-frequency spectrum. Four paths were chosen to allow the use of fewer coefficients than that required by a single path. The microprocessor is used to control the selection of coefficients for each digital filter in order to obtain an overall desired frequency response selected by the users.
Author (s): Riemer, T. E.;
Trahan, R. E.;
Affiliation:
University of New Orleans, New Orleans, LA
(See document for exact affiliation information.)
AES Convention: 74
Paper Number:2045
Publication Date:
1983-10-06
Session subject:
Signal Processing—Digital
DOI:
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Riemer, T. E.; Trahan, R. E.; 1983; Design of a Phase-Linear Digital Audio Equalizer [PDF]; University of New Orleans, New Orleans, LA; Paper 2045; Available from: https://aes.org/publications/elibrary-page/?id=11719
Riemer, T. E.; Trahan, R. E.; Design of a Phase-Linear Digital Audio Equalizer [PDF]; University of New Orleans, New Orleans, LA; Paper 2045; 1983 Available: https://aes.org/publications/elibrary-page/?id=11719
@inproceedings{Riemer1983design,
title={{Design of a Phase-Linear Digital Audio Equalizer}},
author={Riemer, T. E. and Trahan, R. E.},
year={1983},
month={oct},
booktitle={Journal of the Audio Engineering Society},
publisher={Paper 2045; AES Convention 74; October 1983},
number={2045},
organization={AES},
}
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