Processing of digital audio requires extremely high-speed arithmetic operations to be performed. Although the audio samples themselves are 16 bits due to AD and DA converter limitations, 24 bits or more are required for intermediate values and for filter coefficients. There are no commercial integrated circuits of the required speed and width at the current time, although there are many on the horizon. We have designed and had made a pair of gate arrays that realize a 24 bit by 24 bit multiply, followed by a 56-bit accumulator with optional saturation. The circuits utilize a 4-stage pipeline and operate with a 65 nanosecond clock. This allows multiply/accumulate operations to be started at a rate greater than 15 Mhz. The circuits have internal diagnostic paths built-in, so that all pipeline stages may be read out.
(See document for exact affiliation information.)
Click to purchase paper as a non-member or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member Join the AES. If you need to check your member status, login to the Member Portal.
