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Configurable Microprocessor Implementation of Low Bit Rate Audio Decoding

Using a configurable microprocessor to implement low-bit-rate audio applications by tailoring the instruction set reduces algorithm complexity and implementation cost. As an example, this paper describes a Dolby Digital (AC-3) decoder implementation that uses a commercially-available configurable microprocessor to achieve 32-bit floating-point precision while minimizing the required processor clock rate and die size. This paper focuses on how the audio quality and features of the reference decoder algorithm dictate the customization of the microprocessor. This paper shows examples of audio specific extensions to the processor's instruction set to create a family of AC-3 decoder implementations that meet multiple performance and cost points. How this approach benefits other audio applications is also discussed.

Author: Brown, Gary S.
Affiliation: Tensilica, Inc., Santa Clara, CA
AES Convention:113 (October 2002) Paper Number:5689 Import into BibTeX
Subject:Low Bit-Rate Coding

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