A 216kHz single die stereo delta sigma ADC is designed for high precision audio applications. A single loop, fifth-order, thirty-three level delta sigma analog modulator with positive and negative feedforward path is implemented. An interpolated multilevel quantizer with unevenly weighted quantization levels replaces a conventional 5-bit flash type quantizer in this design. These new techniques suppress the signal dependent energy inside the delta sigma loop and reduce internal channel noise coupling. Integrated with an on-chip bandgap reference circuit, DEM(dynamic element matching) circuit and a linear phase, FIR decimation filter, the ADC achieves 124dB dynamic range (A-weighted), –110dB THD+N over a 20kHz bandwidth. Inter-channel isolation is 130dB. Power consumption is approximately 330mW

Authors: Yang, YuQing; Sculley, Terry; Abraham, Jacob
Affiliation: Texas Instruments, Inc.
AES Convention: 123 (October 2007) Paper Number: 7289
Publication Date: October 1, 2007 Import into BibTeX
Subject: Signal Processing
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=14346

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