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Last Updated: 20060821, mei

P16 - Posters: Amplifiers & High Resolution

Saturday, October 7, 1:30 pm — 3:00 pm

P16-1 Digital Correction of Switching Amplifier by Error Remodulation MethodHaekwang Park, Vladislav Shimanskiy, Youngsuk Song, Heesoo Lee, Seongcheol Jang, Samsung Electronics Co. Ltd. - Seoul, Korea
In this paper the error remodulation method for digital correction of a pulse width modulation switching amplifier is proposed. This method extracts an error signal from the difference between the reference pulse width modulation signal and power stage output and generates the error pulse width modulation signal by using a remodulation method. The error pulse width modulation signal is then used to compensate for the power supply noise and nonlinearity of the power stage. The proposed method is suitable for the correction of the PWM controller in a full digital amplifier.
Convention Paper 6946 (Purchase now)

P16-2 Iterative Method for Natural SamplingVladislav Shimanskiy, Seong-cheol Jang, Samsung Electronics Co. Ltd. - Seoul, Korea
The performance of pure digital audio amplifiers using pulse-width modulation highly depends on the conversion accuracy of the pulse-code modulated audio signal into pulse-width modulated sequence. This process implies the recovery of original analog signal values at irregular time instances bearing on a uniformly distributed pulse-code modulated data only. The recovery, or “natural sampling,” requires interpolation processing giving a trade-off between accuracy of the result and computation speed. In this paper we propose a method for natural sampling by providing tunable speed-performance constrains while giving the advantage of easy implementation in VLSI. Cubic polynomial interpolation and iterative solving algorithm, as well as experimental results, are presented in the paper.
Convention Paper 6947 (Purchase now)

P16-3 A High Performance S/PDIF TransceiverPaul Lesso, Wolfson Microelectronics - Edinburgh, Scotland, UK
This paper details the design and implementation of a novel S/PDIF transceiver with a very low jitter bandwidth. We describe and demonstrate a system based on multiple-loops that synchronizes to the incoming data stream with a very low bandwidth and provides the original data unmodified on a clean low jitter output clock without the need for a sample rate converter. Thus we eliminate any jitter above a low frequency (typically 10 Hz) on the input data and also avoid any distortion caused by sample rate converters.
Convention Paper 6948 (Purchase now)

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