AES London 2011
Poster Session P6

P6 - Audio Equipment

Friday, May 13, 16:30 — 18:00 (Room: Foyer)

P6-1 Study and Analysis of the Carrier Distortion Sources in PWM DCI-NPC ModulatorVicent M. Sala, Luis Romeral, UPC-Universitat Politecnica de Catalunya - Terrassa, BCN, Spain
This paper studies and analyzes an analog PWM Modulator for a Half-Bridge DCI-NPC Amplifier (Diode Clamped Inverter - Neutral Point Clamped) as one of the sources of distortion in the switching amplification chain. The four types of error or distortion sources are studied and analyzed: Carriers Offset Error (COE), Carriers Phase Error (CPE), Carriers Symmetry Error (CSE), and Carriers Amplitude Error (CAE). This paper concludes that the two major sources of error or distortion in PWM modulation process for DCI-NPC topology are the Amplitude (CAE) and Offset (COE) Errors, the latter being largest contributor to the total distortion.
Convention Paper 8348 (Purchase now)

P6-2 Experimental Verification of an Electrostatic Transducer with a Partitioned Back ElectrodeLibor Husník, Czech Technical University in Prague - Prague, Czech Republic
Electroacoustic transducers based on the condenser principle have usually a planar back electrode that is a one-piece entity. The previous work studied theoretically the possibility of making the back electrode partitioned. Such an arrangement can be used in a design of the so-called digital loudspeaker, in which the sizes of the partitioned electrode are in the ratio of the powers of 2, but this is only a special case. The aim of this work is to study performance of a system modeling the electrostatic transducer with the partitioned back electrode by way of measurement on an experimental sample. Various combinations of signals are applied on the partitioned electrode and the transducer response is measured.
Convention Paper 8349 (Purchase now)

P6-3 Capacitor “Sound” in Microphone Preamplifier DC Blocking and HPF Applications: Comparing Measurements to Listening TestsRobert-Eric Gaskell, McGill University - Montreal, Quebec, Canada
The sonic effect of capacitors in various aspects of audio electronics design has long been discussed and speculated upon. Recent publications have tested many of these theories through rigorous distortion measurements of a variety of capacitor types under several test conditions. One particularly interesting result is a measurable increase in 2nd harmonic distortion for electrolytic and PET type capacitors when a DC bias is applied. This paper repeats these measurements for a set of capacitors commonly used in +48V blocking applications and high pass filters in microphone preamplifier designs. These physical measurements are then compared to the result of double blind listening tests in order to examine the audibility of these capacitor distortions as well as explore their sonic effect on various program materials.
Convention Paper 8350 (Purchase now)

P6-4 1W 104dBA SNR Filterless Fully-Digital Class D Audio Amplifier with EMI Reduction TechniqueRossella Bassoli, Carlo Crippa, Federico Guanziroli; Germano Nicollini, ST-Ericsson - Agrate Brianza, Monza Brianza, Italy
A 1W filter-less power DAC featuring 104dBA SNR and EMI spreading is presented. Pre-distortion algorithms are used to reduce harmonic distortion inherent to the employed modulation process, and an oversampling noise shaper allows reducing modulator clock speed to facilitate hardware implementation while keeping high-fidelity quality. No analog circuits exist from I2S interface to speaker, leading to zero output offset and good efficiency even at medium/low power levels. 1.2V digital and 2.7V-5V output supplies are used. Active area is 0.94mm2 in a 0.13micron CMOS process. Total harmonic distortion at maximum level is about 0.2%.
Convention Paper 8351 (Purchase now)

P6-5 Ultra-Low Power Audio Architecture for Portable DevicesKangeun Lee, Changyong Son, Dohyung Kim, Sihwa Lee, Samsung Advanced Institute of Technology - Suwon, Korea
Current portable devices demand not only higher performance but also lower power consumption. For the reason, this paper describes a low power System-on-Chip (SoC) architecture that targets playback multimedia format. To significantly reduce power consumption of the SoC, the system exploits a DSP core to decode compressed audio. It is a key technique that a pre-buffer keeps compressed audio data. Therefore, the DSP can independently playback audio data, and other systems including CPU, and DRAM is able to be power off until all audio data remaining in the pre-buffer is exhausted by the DSP. For seamless operation, we designed a new kernel driver that controls the DSP and CPU, and it is embedded into Linux kernel sets of the Google’s Android 2.2. Energy efficiency is evaluated by using fourteen audio sequences encoded with mp3 of which format is 128kbps stereo. The experimental results show that the proposed system required only 25% power of the conventional DVFS algorithm and guaranteed Quality of Service (QoS) for mp3 playing.
Convention Paper 8352 (Purchase now)

P6-6 Design of a Passive DGRC Column Loudspeaker with Wave Front SynthesisXavier Meynial, Gilles Grégoire, Active Audio - Saint-Herblain, France
The DGRC (Digital and Geometric Radiation Control) principle allows one to assign a large number of loudspeakers of a line array to a limited number of electronic channels. It was introduced in 2006 and is now used in digitally steerable column loudspeakers. In this paper we propose a very simple and straightforward implementation of this principle in a passive column, where delays are approximated with all-pass passive circuits. As a result, the column is placed vertically (not tilted) and radiates a wave front that ensures high speech intelligibility and homogeneous SPL coverage. We present the design of this column, as well as experimental results. Finally, we discuss its advantages in terms of visual integration, acoustic performances, and cost effectiveness.
Convention Paper 8353 (Purchase now)

P6-7 Design and Realization of a Reference Class Loudspeaker Panel for Wave Field SynthesisStephan Mauer, Frank Melchior, IOSONO GmbH - Erfurt, Germany
This paper describes the requirements, the design, and the realization of a reference loudspeaker panel for Wave Field Synthesis (WFS). Beside the algorithm and the loudspeaker's acoustical performance the quality of Wave Field Synthesis is strongly dependent on the spatial aliasing frequency. Only below that frequency will the synthesized wave field be physically correct. The spatial aliasing frequency is related to the distance of adjacent speakers in the loudspeaker array. To raise the aliasing frequency to 2.8 kHz a loudspeaker panel was designed with a tweeter spacing of 6 cm. The transducers, electronics, and directivity were designed to obtain an excellent sound quality and SPL coverage. Simulations regarding the influence of speaker spacing and wave field artifacts have been made. Measurement results of the panel are given. The overall system design will be shown as an application example.
Convention Paper 8354 (Purchase now)

P6-8 Study and Analysis of Demodulation Filter Losses in DCI-NPC Multilevel Power AmplifiersVicent M. Sala, Luis Romeral, UPC-universitat Politecnica de Catalunya - Terrassa, BCN, Spain
This paper presents a less studied source of efficiency losses in Multilevel Diode-Clamped-Inverter or Neutral-Point-Converter (DCI-NPC) Power Switching Amplifiers. Filter inductors generally add another significant contribution to the total power loss in Power Switching Amplifiers systems. This contribution is generally comparable to that of the switching power stage and it is important to obtain a reasonable accurate estimate of the losses. In this paper the four possible sources of losses in the demodulation filter are studied and analyzed and are defined the expressions to calculate the value of the losses. Using these loss expressions, this paper analyzes the contribution of each of the sources. This work finishes up presenting the results of simulation and the conclusions.
Convention Paper 8355 (Purchase now)

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