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v7.0, 20040922, me

Sunday, October 31, 9:30 am – 11:30 am
Session Z7 Posters: SIGNAL PROCESSING, Part 1
NOTE: During the first 10 minutes of the session all authors will present a brief outline of their presentation.

9:30 am
High-Ordered Adaptive FIR Filters for Acoustical Echo CancellationDevon A. Bergman, Dolby Laboratories, San Francisco, USA; Michael Scordilis, University of Miami, Miami, FL, USA
A common problem in acoustical echo cancellation is the continuous change in the room’s impulse response. These changes need to be monitored and adapted to in order to create an enjoyable echo-free environment. In the experiment proceeding, measurements were taken to find an optimal FIR filter that would allow for fast convergence of the adaptive filter as well as a significant echo return loss. Finally, considerations were also taken to create a smooth adaptation from one configuration to the next.
Convention Paper 6299

9:30 am
Z7-2 Class D Amplifier with Zero Switching Ripple
Eric Mendenhall, Audio Power Electronics, Dove Canyon, CA, USA
Class D amplifiers are used for their high efficiency, but they have some undesirable characteristics, one of these being the residual switching frequency ripple. This paper shows a method of switching frequency ripple reduction by means of ripple steering. With this technique a second output is constructed, into which the switching ripple is steered, substantially relieving the main output from a major artifact of Class D operation.
Convention Paper 6300

9:30 am
FPGA Implementation of an Audio ProcessorSevag Balkorkian, American University of Beirut, Beirut, Lebanon
Implementing hardware design in Field Programmable Gate Arrays (FPGA) is a formidable and an interesting task especially when considering digital signal processing (DSP) applications. Hardware design skills and strong background in signal processing are required. Sometimes problems arise in realizing hardware implementation for a simple design of systems where the theoretical concept is plausible; care should be taken to account for minute design details. The objective of this paper is to present the design of a digital audio signal processor that performs multi-effect processing and, at the same time, is capable of real time configurability on a single FPGA chip. The design is specific to certain algorithmic tasks; there is no need for general purpose architecture and it can be characterized as a system on chip application. It is configurable and able to change coefficients utilizing Look up Tables and is capable of performing filtering and echo/delay generation.
Convention Paper 6301

9:30 am
Real-Time Power Supply Compensation for Noise-Shaped Class D AmplifierLingli Zhang, John Melanson, Johann Gaboriau, Mel Hagge, Randy Boudreaux, Cirrus Logic, Austin, TX,
This paper presents a pure digital real-time power supply compensation scheme for both single-ended and bridge tied-load configured noise-shaped class D amplifiers. Using the appropriate power supply measurement circuitry, the scaled AC and DC components of the power supply voltage rail(s) are fed back into the PWM controller to modify the feedback path and the direct path of the noise shaper. All delays through the feedback loop have been minimized such that the ripple cancellation of the output stage is accomplished in real time. A two-chip ADC/PWM controller with this compensation scheme achieves 40dB power supply rejection of a 60Hz ripple and 100dB system dynamic range.
Convention Paper 6302

9:30 am
Digital Audio Power Amplifier for DSD Data StreamsFrancis Prime, KEF Audio, Maidstone, Kent, UK; Malcolm Hawksford, University of Essex, Colchester, Essex, UK
A digital power amplifier topology is proposed optimized specifically for use with DSD-type data streams. The configuration enables direct interfacing of DSD data with no requirement for intermediate signal processing or analogue-to-digital conversion. The output architecture exploits a classic H-bridge configuration and uses a novel form of ac data coupling to simplify internal interface circuitry. Wide range gain control is enabled through modulation of the output-stage power supply voltage that also improves power efficiency at low gain settings. Consideration is given to finite pulse rise time and a modified DSD data format is investigated.
Convention Paper 6303

9:30 am
Implementation of High-Order Convolution Algorithms with Low Latency on Silicon ChipsRolf Anderegg, Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland; Uli Franke, Weiss Engineering Ltd., Zurich, Switzerland, Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland; Norbert Felber, Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland; Wolfgang Fichtner, Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland
Audio signal processing often requires modeling of large rooms (e.g., churches) with impulse responses of several seconds duration. Direct convolution of the sound stream with such long responses exceeds the capacity of common signal processors by far. Using the Fast Fourier Transform instead reduces the number of operations logarithmically but introduces unacceptable latency. Segmenting the processing into initial short blocks and subsequent longer ones lets one trade latency versus computation power as presented in previous AES papers. Hardware-wise the reduction of operations comes at the cost of large storage with high memory bandwidths. Dedicated application-specific integrated circuits (ASIC) are predestined to perform the rather regular processing, freeing the processors for other tasks. This paper shows suitable architectures for integration on silicon of optimized fast-convolution algorithms. Possible optimizations for fast-convolution algorithms are examined. Based on these findings different architectures for integration on ASIC/FPGA (Field Programmable Gate Array) of such algorithms are developed, analyzed, and compared. The paper is concluded by presenting an exemplary ASIC implementation.
Convention Paper 6304

9:30 am
Scalability in the Modified Discrete Cosine Transform Filter BankChu-Jae Yoo, LG Electronics, Seoul, Korea; Hyung-Myung Kim, KAIST, Taejon, Korea
Modified Discrete Cosine Transform (MDCT) filter bank, or often called the Time Domain Aliasing Cancellation (TDAC) filter bank, is widely used in audio coding systems. The last step of the conventional MDCT filter bank is the dual overlap add procedure to restore an uncompressed original signal. The last step can be generalized using the multiple overlap add procedure, in which the input and output block size can be reduced as the number of overlapped windows increases. The MDCT system with multiple overlap add can reveal scalability features in proportion to the number of overlapped windows when it is used along with the fixed bit adaptive quantization capable of maintaining nearly the same SNR irrespective of the input level. It has been shown that the proposed structure is scalable in block units with the same data rate as the conventional system, and that it shows slight SNR improvement over conventional one.
Convention Paper 6305

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