This paper describes a class D amplifier topology with digital input and a digital compensation loop filter to improve linearity. The core of the system is a high resolution hybrid multi-bit SigmaDelta-Pulse Width Modulation (PWM) modulator without the need for Dynamic Element Matching (DEM). Furthermore, high frequency DSP algorithms to correct for PWM distortion are not required. A system prototype based on a FPGA and commercial 16b analog to digital converter (ADC) validate the system design before implementation in 0.13um CMOS. Measurement results at 1 kHz yield a Total Harmonic Distortion (THD) better than 0.03% and greater than 30 dB of noise rejection. The system is inherently scalable to deep submicron processes due to its predominately digital architecture. To reduce power consumption a low power ADC design is presented.