Last Updated: 20060821, mei
P1 - Digital Amplifiers
Thursday, October 5, 9:00 am — 11:30 am
Chair: Bob Adams
P1-1 CMOS Class D Amplifier with Output Optimization—Dan White, Sina Balkir, Michael Hoffman, University of Nebraska-Lincoln - Lincoln, NE, USA
Simple amplifier topologies are not the norm for integrated circuit (IC) class D amplifiers. A simple self-oscillating topology is mapped into a standard CMOS technology and fabricated in a 0.5 micron process. The output stage is optimized for a range of modulation indices, simultaneously increasing average efficiency and reducing chip area. Modifications to the optimization methodology are proposed to enhance efficiency and reduce the large transient currents inherent in CMOS inverter chains. Test results are presented and compared to predicted and simulated values. This project shows that design complexity is not requisite for good performance and high efficiency.
Convention Paper 6859 (Purchase now)
P1-2 A Digital Class-D Amplifier with Power Supply Correction—Jeroen Tol, Robert Rutten, Derk Reefman, Philips Research Laboratories - Eindhoven, The Netherlands; Arnaud Biallais, Lûtsen Dooper, Jeroen van den Boom, Philips Semiconductors - Nijmegen, The Netherlands; Renaud de Saint-Moulin, Philips Applied Technologies - Leuven, Belgium; Bruno Putzeys, Hypex Electronics - Groningen, The Netherlands; Frans de Buys, Philips Software - Leuven, Belgium
Digital class-D amplifiers are cost-effective solutions for a wide range of digital audio applications because of their high power efficiency and ease of integration. This paper presents a real-time cost-effective power supply correction algorithm, which increases the power supply rejection of an open-loop digital class-D amplifier substantially. It enables open-loop digital class-D amplifiers with inexpensive power supplies with less decoupling. Measurements on a prototype amplifier with single-ended loudspeaker loads show 57 dB suppression for 100 Hz supply ripple, while intermodulation products between a 100 Hz supply ripple and a 1 kHz audio tone are attenuated with 40 dB. The dynamic range of the amplifier is 96 dB, which is in agreement with jitter calculations and measured phase noise of the on-chip clock generator.
Convention Paper 6860 (Purchase now)
P1-3 Automotive Class D Digital Amplifier Output Stage—Brad Stewart, Freescale Semiconductor - Chandler, AZ, USA; Jim Lee, Freescale Semiconductor - Tempe, AZ, USA; Daniel Wildhaber, Freescale Semiconductor - Ridgeland, MI, USA; Ondrej Pauk, Freescale Semiconductor - Tempe, AZ, USA; Richard Deken, James Babb, Freescale Semiconductor - Ridgeland, MI, USA
Automotive applications using class D digital PWM switching amplifiers have long been limited by the approach’s perceived higher cost, the potential for radiated electromagnetic interference affecting in-vehicle electronics, and the difficulties of designing this type of amplifier using discrete components. An integrated circuit built on a high performance analog mixed signal plus power silicon process coupled with innovative circuit design now allows the deployment of high power class D amplifiers in vehicles that had previously been confined to only class AB amplifier designs. Class D PWM amplifiers, switching to 400 kHz or more, can achieve an unweighted dynamic range in exceeding 100 dB, linearity in excess of 80 dB, and PSRR greater than 80 dB with a full scale audio signal.
Convention Paper 6861 (Purchase now)
P1-4 High Performance Digital Feedback for PWM Digital Audio Amplifiers—Pallab Midya, Bill Roeckner, Theresa Paulo, Freescale Semiconductor - Lake Zurich, IL, USA
Non-idealities associated with the power stage of pulse width modulated (PWM) based, open loop digital audio amplifiers limit their performance. A high performance digital feedback system corrects for both power supply noise and power stage nonlinearity in a PWM digital audio amplifier. An integrated circuit (IC) implementation of this system, along with measured results, is presented. The PWM amplifier, switching between 300 kHz and 400 kHz, achieves an unweighted dynamic range in excess of 100 dB, linearity in excess of 80 dB, and excellent power supply rejection (PSR) with a large scale audio signal.
Convention Paper 6862 (Purchase now)
P1-5 Asynchronous Sample Rate Converter for Digital Audio Amplifiers—Pallab Midya, Bill Roeckner, Freescale Semiconductor - Lake Zurich, IL, USA; Tony Schooler, Motorola, Inc. - Schaumburg, IL, USA
A high performance digital audio amplifier system requires an asynchronous sample rate converter to synchronize the input digital data stream to the low jitter system clock used to generate the digital pulse width modulated (PWM) output. By performing the sample rate conversion with highly oversampled signals the computation and memory requirements are minimized. The performance of the digital amplifier system is not limited by the sample rate converter, while accommodating multiple input and output rates. The digital amplifier system, including the asynchronous sample rate converter, is implemented in an IC. Measured data shows linearity performance exceeding 120 dB.
Convention Paper 6863 (Purchase now)