120th AES Convention - Paris, France - Dates: Saturday May 20 - Tuesday May 23, 2006 - Porte de Versailles

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AES Paris 2006

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Last Updated: 20060508, mei

P8 - Signal Processing and High Resolution Audio, Part 1

Sunday, May 21, 08:40 — 12:20

Chair: Pauli Minaar, AM3D A/S - Aalborg, Denmark

P8-1 All Amplifiers Are Analog, but Some Amplifiers Are More Analog than OthersBruno Putzeys, Hypex Electronics B.V. - Groningen, The Netherlands; André Veltman, Paul van der Hulst, Piak Electronic Design b.v. - Culemborg, The Netherlands; René Groenenberg, Mueta b.v. - Wijk en Aalburg, The Netherlands
This paper intends to clarify the terms “digital” and “analog” as applied to class-D audio power amplifiers. Since loudspeaker terminals require an analog voltage, an audio power amplifier must have an analog output. If its input is digital, digital-to-analog conversion is necessarily executed at some point. Once a designer acknowledges the analog output properties of a class-D power stage, amplifier quality can improve. The incorrect assumption that some amplifiers are supposedly digital, causes many designers to come up with complicated patches to ordinary analog phenomena such as timing distortion or supply rejection. This irrational approach blocks the way to a rich world of well-established analog techniques to avoid and correct many of these problems and realize otherwise unattainable characteristics such as excellent THD+N and extremely low output impedance throughout the audio band.

[Associated Poster Presentation in Session P17, Monday, May 22, at 09:00]

Presentation is scheduled to begin at 08:40
Convention Paper 6690 (Purchase now)

P8-2 Toward an Ideal Switching (Class-D) Power Amplifier: How to Control the Flow of Power in a Switching Power CircuitRolf Esslinger, Dieter Jurzitza, Harman/Becker Automotive Systems - Karlsbad, Germany
The design of a switching (class-D) audio power amplifier suitable for high-end audio applications is still a very challenging task for circuit design and signal processing engineers. Classical power stage topologies using Pulse-Width Modulation (PWM) in combination with voltage-controlled MOSFET H-bridges are already available on the market, but their performance in terms of signal bandwidth and linearity is still far below the one of traditional class-A and A/B power stages. Moreover, EMC is an issue that is very hard to control. Class-D output stages are considered from a totally different point of view in this paper. The flow of power in the output stage, containing the switching power stage as a power control element, the output filter as an energy store, and the load as both a power sink and a power source in case the load is not a resistor but a real world loudspeaker device. It is shown, where in a typical power stage the power loss occurs, which is dissipated as heat. To improve the quality and efficiency of high-frequency switched power stages, investigation has to be taken into the way, how to control the flow of power into the storage elements and how to charge them most precisely and most efficiently. Some fundamental approaches for this will be shown in this paper.

[Associated Poster Presentation in Session P17, Monday, May 22, at 09:00]

Presentation is scheduled to begin at 09:00
Convention Paper 6691 (Purchase now)

P8-3 Second Generation Intelligent Class D Amplifier Controller Integrated Circuit Enables both Low Cost and High Performance Amplifier DesignsJack Andersen, Daniel Chieng, Steven Harris, Jeff Klaas, Michael Kost, Skip Taylor, D2Audio Corporation - Austin, TX, USA
This paper describes a digital input Class D amplifier controller integrated circuit that performs many of the functions needed to build a high-performance Class D audio amplifier. Sophisticated digital pulse width modulation, combined with digital feed-forward and feedback paths, yields both low cost and high performance amplifier designs. A powerful DSP is included to support amplifier control and allows comprehensive audio signal processing, including loudspeaker load compensation, EQ, time alignment, room acoustics compensation, bass enhancement, loudspeaker driver protection, virtual surround, and other audio signal processing tasks. Power supply feed-forward and closed-loop feedback technology correct for power supply variations, nonlinearity, and other distortion-inducing mechanisms.

Presentation is scheduled to begin at 09:20
Convention Paper 6692 (Purchase now)

P8-4 PWM Amplifier Control Loops with Minimum Aliasing DistortionLars Risbo, Texas Instruments Denmark A/S - Lyngby, Denmark; Claus Neesgaard, Texas Instruments Inc. - Dallas, TX, USA
PWM class-D audio power amplifiers typically contain a control loop filter network and a comparator producing the PWM signal. The comparator performs a sampling operation whenever it changes state. A previous paper by the author analyzed this sampling behavior from a small signal point of view. The present paper attempts to formulate a large-signal model that accounts for the nonlinear effects of the sampling due to aliasing of high frequency carrier components. Closed-form expressions for the intrinsic THD of the traditional first- and second-order loops are derived. The model is validated using simulations, and a class of Minimum Aliasing Error (MAE) loop filters is presented that obtains minimum aliasing distortion thanks to the use of quadrature sampling. Finally, measurement data are presented for real applications using the principles described.

[Associated Poster Presentation in Session P17, Monday, May 22, at 09:00]

Presentation is scheduled to begin at 09:40
Convention Paper 6693 (Purchase now)

P8-5 Simple, Ultralow Distortion Digital Pulse Width ModulatorBruno Putzeys, Hypex Electronics BV - Groningen, The Netherlands
A core problem with digital pulse width modulators is that effective sampling occurs at signal-dependent intervals, falsifying the z-transform on which the input signal and the noise shaping process are based. In a first step the noise shaper is reformulated to operate at the timer clock rate instead of the pulse repetition frequency. This solves the uniform/natural sampling problem, but gives rise to new nonlinearities akin to ripple feedback in analog modulators. By modifying the feedback signal such that it reflects only the modulated edge of the pulse train this effect is practically eliminated, yielding vastly reduced distortion without increasing complexity.

[Associated Poster Presentation in Session P17, Monday, May 22, at 09:00]

Presentation is scheduled to begin at 10:00
Convention Paper 6694 (Purchase now)

P8-6 A High Performance Open Loop All-Digital Class-D Audio Power Amplifier Using Zero Positioning Coding (ZePoC)Olaf Schnick, Wolfgang Mathis, University of Hannover - Hannover, Germany
Open loop all-digital Class-D amplifiers are uncommon due to the lack of the correcting feedback path leading to several problems resulting in high distortion compared to analog controlled class-D amplifiers. This paper shows that SB-ZePoC lowers switching frequency to 100 kHz. Therefore, these problems can be solved, so that it is possible to design an open loop all-digital class-D audio amplifier with low total distortions in the whole audio-band (20 Hz to 20 kHz) and an efficiency that reaches 90 percent. Results of a test-setup will be presented. The sonic performance will be demonstrated during the session.

[Associated Poster Presentation in Session P17, Monday, May 22, at 09:00]

Presentation is scheduled to begin at 10:20
Convention Paper 6695 (Purchase now)

P8-7 A Three-Level Trellis Noise Shaping Converter for Class D AmplifiersLudovico Ausiello, Riccardo Rovatti, University of Bologna - Bologna, Italy; Gianluca Setti, University of Ferrara - Ferrara, Italy
Class D amplifiers can represent signals with three different output levels, +Vcc, 0, -Vcc, with no distortion. Exploiting this in order to achieve a better performance with no switching frequency increase, an extension to the classic pulse width modulation two level A/D conversion is proposed. Coding is achieved by extending output waveforms of a trellis-based sigma delta modulation to three levels. Simulation results have shown that, using the same symbol rate, a three-level pattern is achieved from 3.7 to 8.2 dB of SINAD improvement and a power consumption up to 5 times smaller.

[Associated Poster Presentation in Session P17, Monday, May 22, at 09:00]

Presentation is scheduled to begin at 10:40
Convention Paper 6696 (Purchase now)

P8-8 Using SIP Techniques to Verify the Trade-Off between SNR and Information Capacity of a Sigma Delta ModulatorCharlotte Yuk-Fan Ho, Joshua Reiss, Queen Mary, University of London - London, UK; Bingo Wing-Kuen Ling, King’s College London - London, UK
The Gerzon-Craven noise shaping theorem states that the ideal information capacity of a sigma delta modulator design is achieved if and only if the noise transfer function (NTF) is minimal phase. In this paper it is found that there is a trade-off between the signal-to-noise ratio (SNR) and the information capacity of the noise shaped channel. In order to verify this result, loop filters satisfying and not satisfying the minimal phase condition of the NTF are designed via semi-infinite programming (SIP) techniques and solved using dual parameterization. Numerical simulation results show that the design with a minimal phase NTF achieves near the ideal information capacity of the noise shaped channel, but the SNR is low. On the other hand, the design with a nonminimal phase NTF achieves a positive value of the information capacity of the noise shaped channel, but the SNR is high. Results are also provided that compare the SIP design technique with Butterworth and Chebyshev structures and ideal theoretical SDMs, and evaluate the performance in terms of SNR and a variety of information theoretic measures which capture noise shaping qualities.

[Associated Poster Presentation in Session P17, Monday, May 22, at 09:00]

Presentation is scheduled to begin at 11:00
Convention Paper 6697 (Purchase now)

P8-9 Estimation of Initial States of Sigma-Delta ModulatorsCharlotte Yuk-Fan Ho, Queen Mary, University of London - London, UK; Bingo Wing-Kuen Ling, King’s College London - London, UK; Joshua Reiss, Queen Mary, University of London - London, UK
In this paper an initial condition of a sigma-delta modulator is estimated based on quantizer output bit streams and an input signal. The set of initial conditions that generate a stable trajectory is characterized. It is found that this set, as well as the set of initial conditions corresponding to the quantizer output bit streams, are convex. Also, it is found that the mapping from the set of initial conditions to the stable admissible set of quantizer output bit streams is invertible if the loop filter is unstable. Hence, the initial condition corresponding to given stable admissible quantizer output streams and an input signal is uniquely defined when the loop filter is unstable, and a projection onto convex set approach is employed for approximating the initial condition.

[Associated Poster Presentation in Session P17, Monday, May 22, at 09:00]

Presentation is scheduled to begin at 11:20
Convention Paper 6698 (Purchase now)

P8-10 High Performance Real-Time Software Asynchronous Sample Rate Converter KernelThierry Heeb, Anagram Technologies - Préverenges, Switzerland
A scalable real-time asynchronous sample rate converter software kernel is presented that offers a flexible alternative to the usual hardware implementations. The kernel is dynamically configurable at run-time and supports almost arbitrary upsampling or downsampling ratios and any number of channels. Due to its scalability this sample rate converter kernel may be used both for low complexity, cost-sensitive implementations as well as for top-performance applications. In a typical high performance application, sample rates of 384 kHz are easily achieved on a low-cost DSP, and DSD input data streams are also supported for compatibility with SACD.

Presentation is scheduled to begin at 11:40
Convention Paper 6699 (Purchase now)

P8-11 Clean Clocks, Once and for All?Christian G. Frandsen, TC Electronic A/S - Risskov, Denmark; Chris Travis, Sonopsis Ltd. - Wotton-under-Edge, Gloucestershire, UK
Network-based digital audio interfaces are becoming increasingly popular. But they do pose a significant jitter problem wherever high-quality conversion to/from analog is required. This is true even with networks such as 1394 that provide dedicated support for isochronous flows. Conventional PLL solutions have too-little jitter attenuation, too-much intrinsic jitter, and/or too-narrow a frequency range. More advanced solutions tend to have too-high a cost. A new clocking technology that boasts high performance and low cost is presented. It has been implemented in a recent audio-over-1394 chip. We show comparative performance results and explore system-level implications, including for systems that use point-to-point links such as AES3, SPDIF, and ADAT.

[Associated Poster Presentation in Session P17, Monday, May 22, at 09:00]

Presentation is scheduled to begin at 12:00
Convention Paper 6700 (Purchase now)

  (C) 2006, Audio Engineering Society, Inc.