AES Conventions and Conferences

   Detailed Calendar
         (in Excel)
   Calendar (in PDF)
   Convention Planner
   Surround - Live:
   Paper Sessions
   Tutorial Seminars
   Special Events
   Exhibitor Seminars
         Room A
   Exhibitor Seminars
         Room B
   Technical Tours
   Student Program
   Free Hearing
   Heyser Lecture
   Tech Comm Mtgs
   Standards Mtgs
   Press Information
   Return to 115th

Sunday, October 12 9:00 am – 12:00 noon
Session K Signal Processing for Audio, Part 1

K-1 Dither and Noise Modulation in Sigma Delta ModulatorsJoshua Reiss, Mark Sandler, Queen Mary, University of London, London, UK
In recent years there has been considerable debate over the suitability of 1-bit Sigma-Delta modulation (SDM) for high-quality applications. Much of the debate has centered on whether it is possible to properly dither such a system. It has been shown that dither with a triangular probability distribution should be applied to the quantizer input in a pulse code modulation system. This is not the case for all A/D converters. We show that the dependence of error moments on input is inherently different in sigma delta modulators, and that the effect of dither depends on whether the quantizer is one bit or multibit. These statements are proven for simple SDMs and verified by simulation.

K-2 Stability Analysis of Limit Cycles in High Order Sigma Delta ModulatorsDerk Reefman, Philips Research, Eindhoven, The Netherlands; Joshua Reiss, Queen Mary, University of London, London, UK; Erwin Janssen, Philips Research, Eindhoven, The Netherlands; Mark Sandler, Queen Mary, University of London, London, UK
We present a mathematical framework, based on state space modeling, for the description of limit cycles of sigma delta modulators (SDMs). Using a dynamical systems approach, the authors treat sigma delta modulators as piecewise linear maps. This enables us to find all possible limit cycles that might exist in an arbitrary sigma delta modulator with predefined input. We then focus on a DC input, analyze their stability, and show exactly the amount of dither that is necessary to remove any given limit cycle. Using several different SDM designs, we locate and analyze the limit cycles and thus verify the results by simulation.

K-3 Compression and Decompression of Wavetable Synthesis DataRobert Maher, Montana State University, Bozeman, MT, USA
Table look-up (or wavetable) synthesis methods have been widely used for many years in music synthesizers. Recently wavetable music synthesis has received new interest in the context of mobile applications such as personalized ring tones and pager notification signals. The limited amount of storage and processing available in such mobile devices makes the use of compressed wavetable data desirable. In this paper several issues related to wavetable compression are described, and an efficient compression/decompression method is proposed for reducing the size of wavetable data while maintaining loop continuity and timbral quality.

K-4 Reconfigurable Logic for Audio Signal ProcessingHelen Tarn, Chris Dick, Xilinx, Inc., San Jose, CA, USA
As audio applications become more complex, it is increasingly difficult to realize the signal processing components by traditional DSP microprocessors due to their limited processing capability in terms of arithmetic capacity, datapath precision, and architecture. An alternative based on field programmable gate array (FPGA) technology is proposed, which not only preserves the versatility and flexibility of DSP microprocessors but also has the advantage of a customizable datapath and arbitrary arithmetic precision. This paper presents a case study in which reconfigurable logic technology is employed in designing infinite impulse response (IIR) filter banks. The study’s results show that thousands of second-order filters can be implemented on a single FPGA and demonstrate the potential of reconfigurable logic technology for audio signal processing.

K-5 Discrete-Time Shelf Filter Design for Analog ModelingDavid P. Berners, Jonathan S. Abel, Universal Audio, Inc., Santa Cruz, CA, USA
A method for the design of discrete-time second-order shelf filters is developed which allows the response of an analog-resonant shelf filter to be approximated in the digital domain. For filters whose features approach the Nyquist limit, the proposed method provides a closer approximation to the analog response than direct application of the bilinear transform. Three types of resonant shelf filters are discussed, and design examples are presented.

K-6 High-Performance Configurable Fixed-Point Audio Processor DevelopmentSrikanth Gurrapu, Doug Roberson, Texas Instruments, Inc., Dallas, TX, USA
Recent advances in CMOS VLSI digital technology make it practical now to pack a lot of high performance audio processing into an ASIC. To fully reap the benefits of these semiconductor technological advances, choosing the right architecture for a given application is crucial. Key considerations involve developing an architecture, which provides high audio performance, feature rich options, flexibility to adapt to market demand, and highly efficient processing for a low cost. Architectural considerations are made to allow OEM developers to easily create custom filters and functional configuration settings to accommodate specific needs without any required knowledge of DSP programming.

Back to AES 115th Convention Back to AES Home Page

(C) 2003, Audio Engineering Society, Inc.