Conventional sigma-delta digital-analog converters (DACs) have performance limitations due to the use of switched-capacitor filters. In this design, a continuous-time output stage is used to achieve 112-dB signal-to-noise ratio (SNR) in a small chip area. The problems of jitter sensitivity and rise/fall matching are avoided by using a 6-bit modulator with a segmented scrambling circuit, along with a dual return-to-zero circuit.

Authors: Adams, Robert; Nguyen: , Khiem; Sweetland, Karl
Affiliation: Analog Devices Inc., Wilmington, MA
AES Convention: 105 (September 1998) Paper Number: 4774
Publication Date: September 1, 1998 Import into BibTeX
Subject: Conversion Technology
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=8406

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