Sample Clock Jitter and Real-time Audio Over the IEEE1394 High Performance Serial Bus
The asynchronous clocks within IEEE1394 high performance serial bus present challenges for sample timing recovery in conjunction with the transmission of digital audio. Moreover the systematic nature of the jitter produced means that prototype systems are unlikely to produce worst-case performance. This is analysed and, with jitter audibility models developed elsewhere, a sampling jitter attenuation requirement is estimated.
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