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32-Bit SIMD SHARC Architecture for Digital Audio Signal Processing Applications

This paper examines desirable DSP architectural features to consider for implementation of real time audio applications using a 32-bit Single Instruction Multiple Data (SIMD) DSP based on a Modified Harvard Architecture. This discussion will examine the specific features in this architecture that are desirable for implementing many of today's professional and consumer audio equipment. The first topic covered are the important audio processor-specific characteristics of this SIMD architecture such as data word size, dynamic range/SNR capabilities, memory organization, processor speed, benchmarks and I/0 capabilities. Part Two will highlight a couple of example DSP audio algorithms to demonstrate the benefits of such an architecture which can speed up DSP execution by as much as a factor of 5 over earlier SISD SHARC: architectures.

Authors: Tomarakos, John; Duggan, Colin; Steyerl, Stefan
Affiliation: Analog Devices, Norwood, USA
AES Convention:106 (May 1999) Paper Number:4983 Import into BibTeX
Subject:Signal Processing

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