AES Store

Journal Forum

Reflecting on Reflections - June 2014

Audibility of a CD-Standard A/DA/A Loop Inserted into High-Resolution Audio Playback - September 2007

Quiet Thoughts on a Deafening Problem - May 2014
1 comment

Access Journal Forum

AES E-Library

32-Bit SIMD SHARC Architecture for Digital Audio Signal Processing Applications

This paper examines desirable DSP architectural features to consider for implementation of real time audio applications using a 32-bit Single Instruction Multiple Data (SIMD) DSP based on a Modified Harvard Architecture. This discussion will examine the specific features in this architecture that are desirable for implementing many of today's professional and consumer audio equipment. The first topic covered are the important audio processor-specific characteristics of this SIMD architecture such as data word size, dynamic range/SNR capabilities, memory organization, processor speed, benchmarks and I/0 capabilities. Part Two will highlight a couple of example DSP audio algorithms to demonstrate the benefits of such an architecture which can speed up DSP execution by as much as a factor of 5 over earlier SISD SHARC: architectures.

AES Convention: Paper Number:
Publication Date:

Click to purchase paper or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member and would like to subscribe to the E-Library then Join the AES!

This paper costs $20 for non-members, $5 for AES members and is free for E-Library subscribers.

Learn more about the AES E-Library

E-Library Location:

Start a discussion about this paper!

Facebook   Twitter   LinkedIn   Google+   YouTube   RSS News Feeds  
AES - Audio Engineering Society