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Area Efficient Decimation Filter for an 18-Bit Delta-Sigma Analog-to-Digital Converter

The paper describes a multistage decimation filter which consists of seven-cascaded comb filters and a 50-tap single-stage finite-impulse response filter. A novel, multirate comb filter structure is used to reduce the date path width. The coefficients of the FIR filter are optimally quanticized to canonical-signed-digit form to realize a multiplier-free (shift-and-add) implementation with a single accumulator and a 256Fs master clock.

Authors: Lin, Kun; Paulos, John
Affiliation: Crystal Semiconducter Corporation, Austin, TX
AES Convention:98 (February 1995) Paper Number:3989 Import into BibTeX
Subject:Audio Signal Processing

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E-Library Location: (CD aes13)   /pp9496/pp9502/3949.pdf

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