Some recent sample-rate converters (SRCs) and digital-to-analog converters (DACs) have included circuitry which rejects jitter on the applied word clock signals. Jitter attenuation can lead to audible improvements in the playback material, especially when the word clock is synthesized from a highly jittered recovered clock, such as in DBS systems. A simple numerically controlled oscillator (NCO) digital circuit is presented which can be used to demonstrate the jitter rejection. Results are reviewed.

Author: Wood, M.
Affiliation: Analog Devices Inc., Wilmington, MA
AES Convention: 100 (May 1996) Paper Number: 4261
Publication Date: May 1, 1996 Import into BibTeX
Subject: Signal Processing
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=7515

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