An algorithm for calculating a real-time sampling-rate conversion via low-order polynomial interpolation of a digital signal is described. Modifications to common DSP chip architectures are then suggested which will reduce the computational complexity of the presented algorithm compared to that of the classical algorithm.

Authors: Wise, Duane K.; Barish, Jeffrey; Lindemann, Eric
Affiliation: EuPhonics, Inc., Boulder, CO
AES Convention: 101 (November 1996) Paper Number: 4370
Publication Date: November 1, 1996 Import into BibTeX
Subject: Signal Processing
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=7409

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