An IC that combines the functions of an AES/EBU receiver and asynchronous rate converter has been designed. This IC allows the systems designer to receive an external AES/EBU signal and sync it to an internal crystal-controlled system clock. The IC uses an all-digital AES receiver that can tolerate large amounts of jitter and tracks over a wide and continuous range of sample frequencies. The sample-rate converter uses a new algorithm that employs a noise-shaped clock signal in conjunction with a digital interpolator/decimator.

Authors: Adams, Robert; Nguyen, Khiem; Sweetland, Karl
Affiliation: Analog Devices Semiconductor Inc., Wilmington, MA
AES Convention: 103 (September 1997) Paper Number: 4536
Publication Date: September 1, 1997 Import into BibTeX
Subject: Signal Processing and Conversion
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=7243

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