Pulse Edge Delay Error Correction (PEDEC)-A Novel Power Stage Error Correction Principle for Power Digital-Analog Conversion
A novel pulse referenced error correction principle for digital to power conversion systems (Power DAC) is proposed-Pulse Edge Delay Error Correction (PEDEC). The method uses a digital pulse modulated signal as reference for error correction. The advantage of PEDEC is a combination of efficient correction of all power stage generated errors, and simple implementation. The paper presents the basic theory of PEDEC, modeling of the principle, and systematic approaches to PEDEC based amplifier design. The theoretical treatment is supplemented with a comprehensive, low level system simulation, that verify the system model and furthermore illustrate correction capability towards every error source in a switching power stage. PEDEC is concluded to be a very interesting new approach that could dramatically ease the design of high quality Power DAC's.
Click to purchase paper or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member and would like to subscribe to the E-Library then Join the AES!
This paper costs $20 for non-members, $5 for AES members and is free for E-Library subscribers.