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VLSI Architectures for Asynchronous Sample-Rate Conversion

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The theory of asynchronous sample-rate conversion is presented using both the highly-interpolated signal-processing model as well as the polyphase filter model. A novel closed-loop address-tracking system is disclosed that solves the problem of clock-edge arrival estimation while at the same time providing a low-jitter selection of the current polyphase filter for each sampling instant. The proposed signal-processing algorithm is well-suited to VLSI implementation, with only modest amounts of RAM, ROM, and digital filter hardware required.

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Permalink: http://www.aes.org/e-lib/browse.cfm?elib=6778

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