This paper examines methods of hardware implementation for integer noise shaping using VHDL (the newly recognized standard for hardware description). Methods of integer coefficient calculation will be discussed for accuracy near floating point. The technique reduces the calculation complexity with a view to reducing the silicon area for hardware implementation, while maintaining 24-bit quality in a minimally oversampled output. Performance will be demonstrated using computer simulation. (VHDL: Very high-speed integrated-circuit hardware description language.)

Authors: Clark, I. G.; Hiorns, R. E.; Davies, A. C.
Affiliation: University of London, Department of Electronic and Electrical Engineering, London, United Kingdom
AES Convention: 94 (March 1993) Paper Number: 3568
Publication Date: March 1, 1993 Import into BibTeX
Subject: Digital Signal Processing
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=6594

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