Asynchronous sample-rate conversion requires the solution to four major problems: clock time-of-arrival estimation, reduction of filter coefficients, RAM read/write pointer control, and dynamic filter adaptation for the undersampled case (FSout < FSin). Existing solutions to these problems involve multiple DSP chips with complicated external hardware. Design details of a new one-chip dedicated asynchronous sample-rate converter IC will be presented.

Authors: Adams, Robert W.; Kwan, Tom
Affiliation: Analog Devices Semiconductor, Wilmington, MA.
AES Convention: 94 (March 1993) Paper Number: 3570
Publication Date: March 1, 1993 Import into BibTeX
Subject: Digital Signal Processing
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=6593

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