A novel Sigma-Delta based audio DAC system is presented. The converter operates at only 32-times oversampling (1.4 MHz) and uses an eighth-order Sigma-Delta modulator implemented in a single FPGA circuit. Two different DAC circuits have been implemented: One using switched capacitor charge packets and one using nonreturn to zero pulses. A voltage-controlled Xtal oscillator-based PLL ensures low-jitter sampling clock recovery.

Author: Risbo, Lars
Affiliation: Electronics Institute, Technical University of Denmark, Denmark
AES Convention: 96 (February 1994) Paper Number: 3808
Publication Date: February 1, 1994 Import into BibTeX
Subject: Implementation of Digital Audio Systems
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=6424

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