To achieve a high resolution (>18 bit) in a bit stream digital-to-analog converter, extremely low jitter in the reconstructed signal must be maintained as the bit stream amplitude is independent of signal level. A method of jitter reduction is proposed using a dynamic averaging filter and a comparison using both DSM and PWM source codes made against a stationary filter. Random and coherent noise sources within the filter are compared and methods of lowering sampling clock jitter are discussed.
Click to purchase paper as a non-member or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member and would like to subscribe to the E-Library then Join the AES!
This paper costs $33 for non-members and is free for AES members and E-Library subscribers.