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Dynamic Jitter Filtering in High-Resolution DSM and PWM Digital-to-Analog Conversion

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To achieve a high resolution (>18 bit) in a bit stream digital-to-analog converter, extremely low jitter in the reconstructed signal must be maintained as the bit stream amplitude is independent of signal level. A method of jitter reduction is proposed using a dynamic averaging filter and a comparison using both DSM and PWM source codes made against a stationary filter. Random and coherent noise sources within the filter are compared and methods of lowering sampling clock jitter are discussed.

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Permalink: http://www.aes.org/e-lib/browse.cfm?elib=6421

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