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VLSI Implementation of a Fully Digital Asynchronous Audio Sample-Rate Converter

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A VLSI circuit is presented that performs sampling rate conversion of digital stereo audio signals. Conceptually, the converter interpolates to 4 Ghz, and then decimates to the desired output sampling rate. The chip is intended for 18-bit professional audio applications with arbitrarily varying input and output sampling frequencies from 25 to 70 kHz. Out chip is compared in architecture and performance to the commercial realization presented in (2) (Analog Devices AD1890).

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AES - Audio Engineering Society