A VLSI circuit is presented that performs sampling rate conversion of digital stereo audio signals. Conceptually, the converter interpolates to 4 Ghz, and then decimates to the desired output sampling rate. The chip is intended for 18-bit professional audio applications with arbitrarily varying input and output sampling frequencies from 25 to 70 kHz. Out chip is compared in architecture and performance to the commercial realization presented in (2) (Analog Devices AD1890).

Authors: Rothacher, Fritz; Felber, Norbert
Affiliation: Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich
AES Convention: 96 (February 1994) Paper Number: 3832
Publication Date: February 1, 1994 Import into BibTeX
Subject: Digital Signal Processing
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=6400

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