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High-Performance Jitter-Reduction Circuit for Digital Audio

A high-performance jitter-reduction circuit based on high-order phase-locked-loop technique has been built for digital audio. It provides over 40-dB attenuation for midfrequencies but still maintains over 10-Hz cutoff frequency. By employing a crystal-based voltage-controlled oscillator, very low intrinsic jitter is achieved.

Author: Wong, Wai-Ki
Affiliation: City Polytechnic of Hong Kong, Hong Kong
AES Convention:97 (November 1994) Paper Number:3888 Import into BibTeX
Subject:Analog Signal Processing

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