A chip set has been developed which implements a high-resolution A/D converter using the noise-shaping/digital decimation technique presented in an earlier paper. The chip set consists of a front-end IC to implement the noise-shaping algorithm and a digital decimator IC to reduce the sampling rate. A new method of canceling the effects of digital waveform asymmetry has been developed, resulting in increased resolution. The application circuit in its minimum configuration gives a dynamic range of 108 dB. More complex configurations yield a dynamic range of 114 dB.

Author: Adams, Robert W.
Affiliation: CTI / dbx, Newton, MA
AES Convention: 86 (March 1989) Paper Number: 2762
Publication Date: March 1, 1989 Import into BibTeX
Subject: Digital Signal Recording and Processing
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=5932

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