A chip set has been developed which implements a high-resolution A/D converter using the noise-shaping/digital decimation technique presented in an earlier paper. The chip set consists of a front-end IC to implement the noise-shaping algorithm and a digital decimator IC to reduce the sampling rate. A new method of canceling the effects of digital waveform asymmetry has been developed, resulting in increased resolution. The application circuit in its minimum configuration gives a dynamic range of 108 dB. More complex configurations yield a dynamic range of 114 dB.
This paper costs $33 for non-members and is free for AES members and E-Library subscribers.