AES E-Library

AES E-Library

VLSI Implementation of a One-Stage 64:1 FIR Decimator

Document Thumbnail

Commercially available Delta-Sigma A/D converters decimate a high-rate input signal in multiple steps using several moving average type FIRs. A stereo digital Decimator Chip has been designed and fabricated which reduces the sample rate of a 1 bit input signal by a factor of 64 in one stage, using a 4096 tap lowpass FIR. The chip has been fabricated in 1.6u CMOS, having a die size of 210mil x 262mil (excluding scribe area), and is capable of running at input sample rates up to 3.6mhz. The internal logic of the VLSI is discussed.

AES Convention: Paper Number:
Publication Date:

Click to purchase paper as a non-member or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member and would like to subscribe to the E-Library then Join the AES!

This paper costs $33 for non-members and is free for AES members and E-Library subscribers.

Learn more about the AES E-Library

E-Library Location:

Start a discussion about this paper!

AES - Audio Engineering Society