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VLSI Implementation of a One-Stage 64:1 FIR Decimator

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Commercially available Delta-Sigma A/D converters decimate a high-rate input signal in multiple steps using several moving average type FIRs. A stereo digital Decimator Chip has been designed and fabricated which reduces the sample rate of a 1 bit input signal by a factor of 64 in one stage, using a 4096 tap lowpass FIR. The chip has been fabricated in 1.6u CMOS, having a die size of 210mil x 262mil (excluding scribe area), and is capable of running at input sample rates up to 3.6mhz. The internal logic of the VLSI is discussed.

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Permalink: http://www.aes.org/e-lib/browse.cfm?elib=5717

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