The paper discusses an adaptive filter board that performs more than 170 million-instructions-per-second (MIPS). The board consists of one DSP56001, 24-bit general purpose digital signal processor which performs 13.5 MIPS of algorithmic computations, and sixteen DSP56200 peripherals, each of which performs 10.24 MIPS of algorithm specific computations such as adaptive/nonadaptive finite-impulse-response (FIR) filtering. Moreover, the DSP56200 is cascadable to configure 16 chips into a single long tap transversal filter forming a 4096-tap adative/nonadaptive FIR filter. As an example, the board was configured for a teleconference phone application with acoustic and electric echo cancellers to achieve full-duplex operation. The performance evaluation, detailed schematic diagrams and complete source routines are included.
https://www.aes.org/e-lib/browse.cfm?elib=5609
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