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Switching Limits of High-Power-MOSFETS in Audio Output Stages

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The model introduced here describes the effects of the propagation delay of the gate signal. It may be used to show the effects of the on-chip delay of applied gate voltage on the surface of a single MOSFET (the vertical power MOSFET consists of a large number of paralleled cells) as well as of discrete paralleled devices.

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Permalink: http://www.aes.org/e-lib/browse.cfm?elib=4834

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