The model introduced here describes the effects of the propagation delay of the gate signal. It may be used to show the effects of the on-chip delay of applied gate voltage on the surface of a single MOSFET (the vertical power MOSFET consists of a large number of paralleled cells) as well as of discrete paralleled devices.

Authors: Thoma, J.; Pichler, H.; Pavuza, F.
Affiliation: Technical University, Vienna, Austria
AES Convention: 84 (March 1988) Paper Number: 2569
Publication Date: March 1, 1988 Import into BibTeX
Subject: Audio Circuitry
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=4834

Click to purchase paper as a non-member or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member and would like to subscribe to the E-Library then Join the AES!

This paper costs $33 for non-members and is free for AES members and E-Library subscribers.

Learn more about the AES E-Library

E-Library Location: (CD aes11)   /pp8690/pp8803/2692.pdf

Start a discussion about this paper!