High quality digital audio processor employing extremely effective error correction schemes as an adaptor for VTRs was developed. The format, based on EIAJ standard, features the use of b-Adjacent (8, 6) error correcting code together with CRC. This (8, 6) code can be decoded in more than one way. The authors, after briefing the standard, describe the system design, coding and decoding, error correction capability, error rate measurement, and performance of the processor.

Authors: Ishida, Yoshinobu; Nishi, Seiki; Kunii, Satoshi; Satoh, Takaharu; Uetake, Katsuhito
Affiliations: Products Development Lab, Mitsubishi Electric Corp., Hyogo, Japan ; Koriyama Works, Mitsubishi Electric Corp., Hyogo, Japan(See document for exact affiliation information.)
AES Convention: 64 (November 1979) Paper Number: 1528
Publication Date: November 1, 1979 Import into BibTeX
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=2826

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