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Linearization Technique of the Power Stage in Open-Loop Class D Amplifiers

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An efficient method to linearize the switching (power) stage of open-loop class D amplifiers is presented. This technique has been successfully applied to an open-loop fully-digital PWM class D amplifier designed in a 40 nm CMOS process leading to nearly 15 dB improvement in the Total Harmonic Distortion (THD). Simulated open-loop class D amplifier performance resulted to 105 dBA Signal-to-Noise Ratio (SNR), and 1W output power over 8 Ohm with 90% power efficiency and 0.014% THD.

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Permalink: http://www.aes.org/e-lib/browse.cfm?elib=18183

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