In the last decade, the Power Amplifier applications have used multilevel diode-clamped-inverter or neutral-point-clamped (DCI-NPC) topologies to present very low distortion at high power. In these applications a lot of research has been done in order to reduce the sources of distortion in the DCI-NPC topologies. One of the most important sources of distortion, and less studied, is the reverse recovery time (trr) of the clamp diodes and MOSFET parasitic diodes. Today, with the emergence of Silicon Carbide (SiC) technologies, these sources of distortion are minimized. This paper presents a comparative study and evaluation of the distortion generated by different combinations of diodes and MOSFETs with Si and SiC technologies in a DCI-NPC multilevel Power Amplifier in order to reduce the distortions generated by the non-idealities of the semiconductor devices.

Authors: Sala, Vicent; Resano, Jr., Tomas; Romeral, Jose Luis; Moreno, Jose Manuel
Affiliation: UPC-Universitat Politecnica de Catalunya, Terrassa, Catalunya, Spain
AES Convention: 133 (October 2012) Paper Number: 8720
Publication Date: October 25, 2012 Import into BibTeX
Subject: Amplifiers, Transducers, and Equipment
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=16462

Click to purchase paper as a non-member or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member and would like to subscribe to the E-Library then Join the AES!

This paper costs $33 for non-members and is free for AES members and E-Library subscribers.

Learn more about the AES E-Library

E-Library Location: (CD 133Papers)   /conv/133/8720.pdf

Start a discussion about this paper!