Digital class-D amplifiers are cost-effective solutions for a wide range of digital audio applications, because of their high power efficiency and ease of integration. This paper presents a real-time cost-effective power supply correction algorithm, which increases the power supply rejection of an open-loop digital class-D amplifier substantially. It enables open-loop digital class-D amplifiers with inexpensive power supplies with less decoupling. Measurements on a prototype amplifier with single-ended speaker loads show 57dB suppression for 100Hz supply ripple, while intermodulation products between a 100Hz ripple and a 1kHz tone are attenuated with 40dB. The dynamic range of the amplifier is 94dB, which is in agreement with phase noise measurements on the on-chip clock generator.
Click to purchase paper as a non-member or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member and would like to subscribe to the E-Library then Join the AES!
This paper costs $33 for non-members and is free for AES members and E-Library subscribers.