Simple amplifier topologies are not the norm for integrated circuit (IC) class D amplifiers. A simple self-oscillating topology [1] is mapped into a standard CMOS technology and fabricated in a 0.5 micron process. The output stage is optimized for a range of modulation indices [2], simultaneously increasing average efficiency and reducing chip area. Modifications to the optimization methodology are proposed to enhance efficiency and reduce the large transient currents inherent in CMOS inverter chains. Test results are presented and compared to predicted and simulated values. This project shows that design complexity is not requisite for good performance and high efficiency.

Authors: Balkir, Sina; Hoffman, Michael; White, Dan
Affiliation: University of Nebraska-Lincoln
AES Convention: 121 (October 2006) Paper Number: 6859
Publication Date: October 1, 2006 Import into BibTeX
Subject: Digital Amplifiers
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=13693

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