Many audio algorithms, such as room simulators and reverberators, operating on Digital Signal Processors access large delay buffers in a non-sequential fashion. Generally, these delay buffers are too large to reside in the on-chip memory of the processor, so they must be placed in external, slow memories. Furthermore, the non-sequential accesses present a problem for maintaining high performance. This paper presents a number of methods that may be employed to improve the performance of the memory accesses of such algorithms. Methods examined include the use of direct CPU memory access, hardware data cache, and dedicated Direct Memory Access (DMA) controllers. Additionally, the algorithm, sample block size, delay taps, tap spacing, and buffer size will be examined and performance results will be presented.

Authors: Watson, Matthew A.; Ganju, Vineet; Maur, Gaganjot
Affiliations: Texas Instruments Inc., Stafford, TX ; Texas Instruments (India) Pvt. Ltd., Bangalore, India(See document for exact affiliation information.)
AES Convention: 116 (May 2004) Paper Number: 6090
Publication Date: May 1, 2004 Import into BibTeX
Subject: Signal Processing
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=12729

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