Journal Forum

Synchronized Swept-Sine: Theory, Application, and Implementation - October 2015

Effect of Microphone Number and Positioning on the Average of Frequency Responses in Cinema Calibration - October 2015
1 comment

The Measurement and Calibration of Sound Reproducing Systems - July 2015

Access Journal Forum

AES E-Library

Performance Improvements for Audio Algorithms that Use Non-sequential Memory Accesses on Digital Signal Processors

Document Thumbnail

Many audio algorithms, such as room simulators and reverberators, operating on Digital Signal Processors access large delay buffers in a non-sequential fashion. Generally, these delay buffers are too large to reside in the on-chip memory of the processor, so they must be placed in external, slow memories. Furthermore, the non-sequential accesses present a problem for maintaining high performance. This paper presents a number of methods that may be employed to improve the performance of the memory accesses of such algorithms. Methods examined include the use of direct CPU memory access, hardware data cache, and dedicated Direct Memory Access (DMA) controllers. Additionally, the algorithm, sample block size, delay taps, tap spacing, and buffer size will be examined and performance results will be presented.

AES Convention: Paper Number:
Publication Date:

Click to purchase paper or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member and would like to subscribe to the E-Library then Join the AES!

This paper costs $20 for non-members, $5 for AES members and is free for E-Library subscribers.

Learn more about the AES E-Library

E-Library Location:

Start a discussion about this paper!

Facebook   Twitter   LinkedIn   Google+   YouTube   RSS News Feeds  
AES - Audio Engineering Society