Performance Improvements for Audio Algorithms that Use Non-sequential Memory Accesses on Digital Signal Processors
Many audio algorithms, such as room simulators and reverberators, operating on Digital Signal Processors access large delay buffers in a non-sequential fashion. Generally, these delay buffers are too large to reside in the on-chip memory of the processor, so they must be placed in external, slow memories. Furthermore, the non-sequential accesses present a problem for maintaining high performance. This paper presents a number of methods that may be employed to improve the performance of the memory accesses of such algorithms. Methods examined include the use of direct CPU memory access, hardware data cache, and dedicated Direct Memory Access (DMA) controllers. Additionally, the algorithm, sample block size, delay taps, tap spacing, and buffer size will be examined and performance results will be presented.
Click to purchase paper as a non-member or login as an AES member. If your company or school subscribes to the E-Library then switch to the institutional version. If you are not an AES member and would like to subscribe to the E-Library then Join the AES!
This paper costs $33 for non-members and is temporarily free for AES members.