We present a mathematical framework, based on state space modelling, for the description of limit cycles of Sigma Delta Modulators (SDMs). Using a dynamical systems approach, the authors treat sigma delta modulators as piecewise linear maps. This enables us to find all possible limit cycles that might exist in an arbitrary sigma delta modulator with predefined input. We then focus on a DC input analyse their stability and show exactly the amount of dither that is necessary to remove any given limit cycle. Using several different SDM designs, we locate and analyse the limit cycles and thus verify the results by simulation.
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