A high performance digital audio amplifier system requires an asynchronous sample rate converter to synchronize the input digital data stream to the low jitter system clock used to generate the digital PWM output. By performing the sample rate conversion with highly oversampled signals the computation and memory requirements are minimized. The performance of the digital amplifier system is not limited by the sample rate converter while accommodating multiple input and output rates. The digital amplifier system, including the asynchronous sample rate converter, is implemented in an IC. Measured data shows linearity performance exceeding 120 dB.

Authors: Midya, Pallab; Roeckner, Bill; Schooler, Tony
Affiliations: Freescale Semiconductor Inc.; Motorola, Inc.(See document for exact affiliation information.)
AES Convention: 121 (October 2006) Paper Number: 6863
Publication Date: October 1, 2006 Import into BibTeX
Subject: Digital Amplifiers
Permalink: https://www.aes.org/e-lib/browse.cfm?elib=13697

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